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    A Q&A series from IIT Bombay




    User Last Visited Last Message
    harshatha 01:45:50 Mon, 17 June 2019 01:45
    cadence is reversible
    sonal 01:44:02 Mon, 17 June 2019 01:43
    algorithms representing VLSI circuits
    juhi 01:41:58 Mon, 17 June 2019 01:40
    VLSI design software
    sandesh 01:37:17 Mon, 17 June 2019 01:36
    Mono-stable circuit
    lakshmi 01:32:10 Mon, 17 June 2019 01:31
    system verilog?
    rucha 01:22:51 Mon, 17 June 2019 01:20
    While simulating SRAM cell
    priya 01:16:44 Mon, 17 June 2019 01:15
    understand intuitively
    milan 00:47:17 Mon, 17 June 2019 00:43
    general tool
    nikita 00:29:14 Mon, 17 June 2019 00:28
    grain boundaries
    john 00:20:13 Sun, 16 June 2019 23:16
    different colour keys